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Diffusion Mesa 8a9491058da7

i965/miptree: Zero-initialize CCS_D buffers

Authored by Nanley Chery <nanley.g.chery@intel.com> on May 2 2018, 6:38 PM.

Description

i965/miptree: Zero-initialize CCS_D buffers

Before this patch, the aux_state was actually AUX_INVALID because the BO
was never defined. This was fine on single slice miptrees because we
would fast-clear the resource right after creation. For multi-slice
miptrees on SKL+ however, this results in undefined behavior when
accessing a non-base slice. Here's a specific example:

  1. Fast clear level 0
    • Undefined CCS_D buffer allocated in "PASS_THROUGH" state.
    • Level 0 transitions to the CLEAR state.
  2. Render to level 1
    • Level 1 may have a 2-bit pattern of 2's.
    • Rendering with a 2 in the CCS is undefined.

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

Details

Committed
Nanley Chery <nanley.g.chery@intel.com>May 17 2018, 4:06 PM
Pushed
pmoreauMay 22 2018, 7:03 PM
Parents
rMESA816f2dc67da7: i965/miptree: Fix handling of uninitialized MCS buffers
Branches
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Event Timeline

Nanley Chery <nanley.g.chery@intel.com> committed rMESA8a9491058da7: i965/miptree: Zero-initialize CCS_D buffers (authored by Nanley Chery <nanley.g.chery@intel.com>).May 17 2018, 4:06 PM